This invention relates to a nonvolatile semiconductor memory device, and to a test logic circuit therefore; and more particularly to a test logic circuit which can easily select only those cells having a high level of data storage among a plurality of nonvolatile memory cells and which can be easily formed on the same semiconductor chip together with the nonvolatile memory cells.
Elements including a floating gate composed of a polycrystalline semiconductor layer surrounded by an insulator such as silicon oxide have heretofore been widely utilized as nonvolatile memories. Although these elements are called "nonvolatile", the charge stored in the floating gate leaks gradually over a long period of time. It may be due to its gate structure, electric field and temperature; and also due to the presence of, for example, a path of current leakage. Especially, defects present locally or randomly in the insulator provide the source of the leakage current path, and complete elimination of these defects has been impossible in spite of efforts of those skilled in the art over long years.
Accordingly, it is an important matter how products having a satisfactory memory holding characteristics can be accurately selected.
A selecting test commonly employed heretofore is based on a method in which a semiconductor memory device is tested under a high-temperature condition and the data holding time under a temperature condition lower than the testing temperature is determined by extrapolation on the basis of the activation energy curve. However, this method has had the following limitations and has not been fully satisfactory:
(1) The temperature in the test is limited by the material of the package of the semiconductor memory device and also by the temperature of the PN junction in the semiconductor. The duration of the test must be extended when the test is carried out at a low temperature to avoid the above problem. As a matter of fact, satisfactory estimation of the data holding time has been impossible in view of the allowable temperature range of the plastics widely employed as the material of the package.
This prior art method is based upon a presumption of a level of activation energy. Therefore, in the event of a variation of the presumed activation energy, estimation at high temperatures becomes extremely inaccurate to the extent that the method is not usable anymore.
According to this method, the storage voltage in the memory cell cannot be directly read, and because of the parasitic noise generated from, for example, the input/output resistor, the estimation of the data holding time becomes difficult more and more and the method may not be executed.